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FEDL7022-01-06
1 Semiconductor ML7022-01
Single Rail Dual Channel PCM CODEC
This version: May 2000 Previous version: Sep. 1999
GENERAL DESCRIPTION
The ML7022 is a two-channel single-rail CODEC CMOS IC for voice signals ranging from 300 to 3400Hz. This device contains two-channel analog-to-digital (A/D) and digital-to-analog (D/A) converters on a single chip. The ML7022 is designed especially for a single power supply and low power applications and achieves a reduced footprint. The ML7022 is best suited for line card applications with easy interface to subscriber line interface circuits (SLICs). The SLIC interface latches are embedded onto this CODEC, thus eliminating the need for external components and optimizing board space.
FEATURES
* Single 5 V Power Supply Operation * Using - ADC and DAC Technique * Low Power Consumption 2-Channel Operating Mode: typical: 70 mW max.: 90 mW 1-Channel Operating Mode: typical: 40 mW max.: 55 mW Power Saving Mode: (CPD1 = CPD2 = "0") typical: 9 mW max.: 12.5 mW Power Down Mode: (PDN = "0") typical: 0.05 mW max.: 0.25 mW * ITU-T Companding Law - -law * Built-in Dual 3-bit Latches with CMOS Drive Capability * Serial PCM Interface * Master Clock: 4.096 MHz * Transmission Clocks: 256 to 4096 kbps * Adjustable Transmit Gain * Built-in Reference Voltage Supply * Analog Output can Directly Drive a 600 Line Transformer * Latched Content Echo-back Function * Package Type: 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name: ML7022-01MB)
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1 Semiconductor
BLOCK DIAGRAM
AIN1 RC LPF BPF Compressor TCONT DOUT XSYNC
- AD CONV
GSX1
AIN2 RC LPF BPF Compressor
- AD CONV
GSX2
BCLK RC LPF LPF Expander RSYNC - DA CONV
AOUT1
RCONT RC LPF LPF Expander - DA CONV
DIN
AOUT2
SGC SG Gen. Power Cont. & Clock Gen. LATCH
VDD AG DG
C1A C2A C3A C1B C2B C3B
PDN
FEDL7022-01-06
MCK
ML7022-01
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PIN CONFIGURATION (TOP VIEW)
VDD TEST1 TEST2 AIN1 GSX1 AOUT1 TEST3 AG SGC
1 2 3 4 5 6 7 8 9
30 PDN 29 C1A 28 C2A 27 C3A 26 RSYNC 25 XSYNC 24 DG 23 DOUT 22 DIN 21 BCLK 20 MCK 19 C3B 18 C2B 17 C1B 16 TEST6
AOUT2 10 GSX2 11 AIN2 12 TEST4 13 TEST5 14 VDD 15 30-Pin Plastic SSOP
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PIN DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol VDD TEST1 TEST2 AIN1 GSX1 AOUT1 TEST3 AG SGC AOUT2 GSX2 AIN2 TEST4 TEST5 VDD TEST6 C1B C2B C3B MCK BCLK DIN DOUT DG XSYNC RSYNC C3A C2A C1A PDN Type -- I I I O O I -- O O O I I I -- I O O O I I I O -- I I O O O I Power Supply * Device Test Pin 1 Device Test Pin 2 Channel-1 Transmit Op-amp Input Channel-1 Transmit Op-amp Output Channel-1 Receive Output Device Test Pin 3 Analog Ground Signal Ground Channel-2 Receive Output Channel-2 Transmit Op-amp Output Channel-2 Transmit Op-amp Input Device Test Pin 4 Device Test Pin 5 Power Supply * Device Test Pin 6 C1B Bit Latched Output C2B Bit Latched Output C3B Bit Latched Output Master Clock (4.096 MHz) Shift Clock for the DIN and DOUT Data Input Data Output Digital Ground Transmit Synchronizing Signal Receive Synchronizing Signal C3A Bit Latched Output C2A Bit Latched Output C1A Bit Latched Output Power Down Control Description
* VDD of pin 1 and VDD of pin 15 are connected internally, but these pins must be connected on the printed circuit board.
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition -- -- -- -- Rating -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -55 to +150 Unit V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Analog Input Voltage High Level Input Voltage Low Level Input Voltage MCK Frequency BCLK Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time MCK to BCLK Phase Difference Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time Sync Pulse Width DIN Set-up Time DIN Hold Time Digital Output Load Bypass Capacitor for SGC Symbol VDD TOP VAIN VIH VIL FMCK FBCLK FSYNC DCLK TIR TIF TMB TXS TSX TRS TSR TWS TDS TDH RDL CDL CSG Condition Voltage must be fixed -- Gain = 1 All Digital Input Pins MCK BCLK XSYNC, RSYNC MCK, BCLK All Digital Input Pins MCK, BCLK BCLK to XSYNC XSYNC to BCLK BCLK to RSYNC RSYNC to BCLK XSYNC, RSYNC DIN DIN Pull-up Resistor, DOUT DOUT C1A, C2A, C3A,C1B, C2B, C3B SG to AG Min. 4.75 -40 -- 2.2 0 -0.01% 256 -- 40 -- -- -- 50 50 50 50 1 BCLK 50 50 0.5 -- -- 0.1 Typ. 5.0 -- -- -- -- 4096 -- 8 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.25 +85 3.4 VDD 0.8 +0.01% 4096 -- 60 50 50 50 -- -- -- -- 100 -- -- -- 50 50 -- Unit V C VPP V V kHz kHz kHz % ns ns ns ns ns ns ns s ns ns k pF pF F
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ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 4.75 to 5.25 V, Ta = -40 to +85C) Parameter Symbol IDD1 Condition 2CH Operating Mode, No Signal PDN = "1", CPD1 = CPD2 = "1" 1CH Operating Mode, No Signal PDN = "1", CPD1 = "1", CPD2 = "0" or PDN = "1", CPD1 = "0", CPD2 = "1" Power Saving Mode, PDN = "1", CPD1 = CPD2 = "0" Power Down Mode, PDN = "0" All Digital Input Pins VI = VDD All Digital Input Pins VI = 0 V DOUT, Pull-up = 0.5 k Digital Output Low Voltage VOL C1A, C2A, C3A, C1B, C2B, C3B IOL = 0.4 mA C1A, C2A, C3A, C1B, C2B, C3B IOH = 0.4 mA C1A, C2A, C3A, C1B, C2B, C3B IOH = 50 A DOUT High Impedance State -- Min. -- Typ. 14.0 Max. 18.0 Unit mA
IDD2 Power Supply Current IDD3 IDD4 High Level Input Leakage Current Low Level Input Leakage Current IIH IIL
--
8.0
11.0
mA
-- -- -- -- 0 0 2.5 VDD -0.5 -- --
1.8 0.01 -- -- 0.2 0.2 -- -- -- 5
2.5 0.05 2.0 0.5 0.4 0.4 -- -- 10 --
mA mA A A V V V V A pF
Digital Output High Voltage
VOH
Digital Output Leakage Current Input Capacitance
IO CIN
Analog Interface Characteristics
(VDD = 4.75 to 5.25 V, Ta = -40 to +85C) Parameter SGC Rise Time Symbol TSGC Condition SG to AG 0.1 F Rise time to 90% of max. level Min. -- Typ. -- Max. 10 Unit ms
Transmit Analog Interface Characteristics
(VDD = 4.75 to 5.25 V, Ta = -40 to +85C) Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RINX RLGX CLGX VOGX VOSGX Condition AIN1, AIN2 GSX1, GSX2 with respect to SG *1 Gain = 1 Min. 10 20 -- -1.13 -20 Typ. -- -- -- -- -- Max. -- -- 30 1.13 20 Unit M k pF V mV
*1 0.27 dBm (600) = 3.17 dBm0 (-law) = 2.26 VPP
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Receive Analog Interface Characteristics
(VDD = 4.75 to 5.25 V, Ta = -40 to +85C) Parameter Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RLAO CLAO VOAO VOSAO Condition AOUT1, AOUT2 (each) with respect to SG AOUT1, AOUT2 AOUT1, AOUT2, RLAO = 0.6 k with respect to SG AOUT1, AOUT2 with respect to SG Min. 0.6 -- -1.7 -100 Typ. -- -- -- -- Max. -- 50 1.7 100 Unit k pF V mV
AC Characteristics
(VDD = 4.75 to 5.25 V, Ta = -40 to +85C) Parameter Symbol Loss T1 Loss T2 Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Loss R2 Loss R3 Loss R4 Loss R5 SDT1 SDT2 SDT3 SDT4 SDT5 SDR1 SDR2 SDR3 SDR4 SDR5 GTT1 GTT2 GTT3 GTT4 GTT5 GTR1 GTR2 GTR3 GTR4 GTR5 NIDLET Idle Channel Noise NIDLER -- -- Freq. (Hz) 60 300 1020 3000 3300 3400 100 1020 3000 3300 3400 Condition Level (dBm0) Min. 25 -0.15 0 GSXn to DOUT (Attenuation) -0.15 -0.15 0 -0.15 -0.15 -0.15 0 36 36 36 30 25 36 36 36 30 25 -0.2 -0.2 -0.6 -1.2 -0.2 -0.2 -0.6 -1.2 -- -- Typ. 45 0.15 Reference 0.02 0.1 0.6 0.04 Reference 0.07 0.2 0.6 43 40 38 32 29 42 39 39 33 30 0.02 Reference 0.06 0.4 0.4 0 Reference -0.02 -0.1 -0.2 14 6 Max. -- 0.20 0.20 0.80 0.80 0.2 0.2 0.8 0.8 -- -- -- -- -- -- -- -- -- -- 0.2 0.2 0.6 1.2 0.2 0.2 0.6 1.2 16 dBrnc0 10 dB Unit
Transmit Frequency Response
Receive Frequency Response
0
DIN to AOUTn (Attenuation)
dB
Transmit Signal to Distortion Ratio
1020
Receive Signal to Distortion Ratio
1020
Transmit Gain Tracking
1020
Receive Gain Tracking
1020
3 0 -30 -40 -45 3 0 -30 -40 -45 3 -10 -40 -50 -55 3 -10 -40 -50 -55 --
GSXn to DOUT *2
dB
DIN to AOUTn *2
dB
GSXn to DOUT
dB
DIN to AOUTn
dB
--
AINn = SG *2 AINn to DOUT DIN = 0 code *2 DIN to AOUTn
*2 C-message Filter is used
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AC Characteristics (Continued)
(VDD = 4.75 to 5.25 V, Ta = -40 to +85C) Condition Min. Typ. Max. Unit Level (dBm0) GSXn to DOUT 0.535 0.555 0.574 VDD = 5 V, Ta = 25C Vrms DIN to AOUTn 0.806 0.835 0.864 VDD = 5 V, 0 Ta = 25C -0.3 -- 0.3 VDD = 4.75 to 5.25 V dB Ta = -40 to 85C -0.3 -- 0.3 0 A to A Mode BCLK = 2048 kHz -- -- -- -- -- -- -- -- -- -- -- 75 75 75 30 -- -- -- -- -- 40 50 40 50 20 20 20 20 -- -- 0.58 0.26 0.16 0.02 0.05 0.07 0.00 0.00 0.00 0.09 0.12 83 80 78 32 -37.5 -50 -48 -50 -54 44 55 45 56 -- -- -- -- 4 4 0.6 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 -- -- -- -- -35 -40 -40 -40 -40 -- -- -- -- 100 100 100 1000 -- -- ms
Parameter
Symbol
Freq. (Hz)
AVT Absolute Level (Initial Difference) AVR Absolute level (Deviation of Temperature and power) Absolute Delay AVTT AVRT TD 1020 1020
Transmit Group Delay
Receive Group Delay
Cross Talk Attenuation Discrimination Out of Band Spurious Signal Frequency Distortion Intermoduration Distortion Power Supply Noise Rejection Ratio
Digital Output Delay Time DOUT Operation Delay Time AOUT Signal Output Delay Time
TGD T1 500 TGD T2 600 TGD T3 1000 0 *3 TGD T4 2600 TGD T5 2800 TGD R1 500 TGD R2 600 TGD R3 1000 0 *3 TGD R4 2600 TGD R5 2800 CRT Trans to Receive 1020 0 CRR Receive to Trans CRCH Channel to Channel DIS 4.6 to 72k 0 0 to 4 kHz 300 to OBS 0 4.6 kHz to 1000 kHz 3.4k SFDT 1020 0 0 to 4 kHz SFDR IMDT fa = 470 -4 2 fa - fb fb = 320 IMDR PSRT1 0 to 4k PSRT2 4 to 50k 100 *4 mVrms PSRR1 0 to 4k PSRR2 4 to 50k TSD DOUT TXD1 Pull-up resister = 0.5 k CL = 50 pF and 1 LSTTL TXD2 C1A, C2A, C3A, C1B, C2B, C3B TPDC CL = 50 pF and 1 LSTTL TDDO TDAO Time of operation start after power on Time of base band signal output start after power on
ms
ms
dB dB dB dBm0 dBm0
dB
ns ns ms ms
*3 Minimum value of the group delay distortion *4 The measurement under idle channel noise
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TIMING DIAGRAM
MCK BCLK XSYNC DOUT TXS TXD1 1 2 TSX TWS TSD MSD D2 TXD2 D4 TMB 3 4 5 6 7 8
D3
D5
D6
D7
D8
Figure 1 Transmit Side Timing Diagram
MCK BCLK TRS RSYNC DIN MSD 1 2 TSR TWS TDS D2 TDH D4 TMB 3 4 5 6 7 8
D3
D5
D6
D7
D8
Figure 2 Receive Side Timing Diagram
1 9 17 25 1
BCLK XSYNC
MSD D2 D3 D4 D5 D6 D7 D8 EPD1 EC3A EC2A EC1A MSD D2 D3 D4 D5 D6 D7 D8 EPD2 EC3B EC2B EC1B MSD D2 D3 1 MSD D2 D3
DOUT
CH1 PCM DATA ECHO bits
CH2 PCM DATA ECHO bits
Figure 3 Transmit Side Bit Configuration
1 9 17 25
BCLK RSYNC
MSD D2 D3 D4 D5 D6 D7 D8 CPD1 C3A C2A C1A MSD D2 D3 D4 D5 D6 D7 D8 CPD2 C3B C2B C1B
DIN
CH1 PCM DATA Latch Data CH2 PCM DATA Latch Data CH1 power down control bit CH2 power down control bit
Figure 4 Receive Side Bit Configuration
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1
9
17
25
1
9
17
25
BCLK
1 Semiconductor
XSYNC RSYNC CH2 PCM Control INPUT DATA DATA CH1 PCM Control INPUT DATA DATA CH2 PCM Control INPUT DATA DATA
CH1 PCM Control INPUT DATA DATA
C1A C2A C3A CPD1 D8 D7 D6 D5 D4 D3 D2 MSD
C1B C2B C3B CPD2 D8 D7 D6 D5 D4 D3 D2 MSD
C1A C2A C3A CPD1 D8 D7 D6 D5 D4 D3 D2 MSD
C1B C2B C3B CPD2 D8 D7 D6 D5 D4 D3 D2 MSD
DIN
EC1A EC2A EC3A EPD1 D8 D7 D6 D5 D4 D3 D2 MSD
EC1B EC2B EC3B EPD2 D8 D7 D6 D5 D4 D3 D2 MSD
EC1A EC2A EC3A EPD1 D8 D7 D6 D5 D4 D3 D2 MSD
EC1B EC2B EC3B EPD2 D8 D7 D6 D5 D4 D3 D2 MSD
DOUT
CH1 PCM ECHO OUTPUT DATA BIT TPDC
CH2 PCM ECHO OUTPUT DATA BIT
CH2 PCM ECHO OUTPUT DATA BIT
CH1 PCM ECHO OUTPUT DATA BIT TPDC
C3A, C2A, C1A, C3B, C2B, C1B
FEDL7022-01-06
ML7022-01
Figure 5 Control Bit Timing and Echo Back Timing
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1 Semiconductor
PDN
SGC TSGC
CPD1 (CPD2)
DOUT TDDO High Impedance
AOUTn TDAO
SG Level
Figure 6 SGC, DOUT and AOUT Output Timing
FEDL7022-01-06
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FUNCTIONAL DESCRIPTION
Pin Functional Description AIN1, AIN2, GSX1, GSX2 AIN1 and AIN2 are the transmit analog inputs for Channels 1 and 2. GSX1 and GSX2 are the transmit level adjustments for Channels 1 and 2. AIN1 and AIN2 are inverting inputs for the op-amp; GSX1 and GSX2 are connected to the output of the op-amp and are used to adjust the level, as shown below. If AIN1 and AIN2 are not used, connect AIN1 to GSX1 and AIN2 to GSX2. During power saving and power down mode, the GSX1 and GSX2 outputs are at AG voltage. In the case of the analog input 2.26 Vpp at GSX pin with digital output +3.17 dBm0 (-law).
GSX1 R2 CH1 Analog Input C1 R1 SG GSX2 R4 CH2 Analog Input C2 R3 SG AIN2 AIN1
CH1 Gain Gain = R2/R1 10 R1: Variable R2 > 20 k C1 > 1/ (2 x 3.14 x 30 x R1) CH2 Gain Gain = R4/R3 10 R3: Variable R4 > 20 k C2 > 1/ (2 x 3.14 x 30 x R3)
AOUT1, AOUT2 AOUT1 is the receive analog output for Channel 1 and AOUT2 is used for Channel 2. The output signal has an amplitude of 3.4Vpp above and below the signal ground voltage (SG).When the digital signal of +3.17 dBm0 is input to DIN, it can drive a load of 600 or more. During power saving or power down mode, these outputs are at a high impedance. VDD Power supply for +5 V. Connect a bypass capacitor of 0.1 F with excellent high frequency characteristics between this pin and the AG pin. Although VDD pin 1 and VDD pin 15 are connected internally, these pins must be connected on the printed circuit board.
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AG Ground for the analog signal circuits. DG Ground for the digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground. SGC Used to generate the signal ground voltage level, by connecting a bypass capacitor. Connect a 0.1 F capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. During power down mode, this outputs are at the voltage level of AG with about 50 k impedance. MCK Master clock input. The frequency must be 4.096 MHz. BCLK Shift clock signal input for the DIN and DOUT signals. The frequency, equal to the data rate, is 256 k to 4096 kHz. This signal must be synchronized in phase with the MCK (generated from the same clock source as MCK). Figure 1 shows the phase difference of MCK and BCLK. RSYNC Receive synchronizing signal input. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the MCK (generated from the same clock source as MCK). XSYNC Transmit synchronizing signal input. The PCM output signal from the DOUT pin is output in synchronization with this transmit synchronizing signal. This synchronizing signal synchronizes all timing signals of all section. This signal must be synchronized in phase with the MCK (generated from the same clock source as MCK).
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DIN DIN is a data input pin. The voice band signal is converted to an analog signal in synchronization with the RSYNC signal and BCLK. The analog signal of channel 1 is output from AOUT1 pin and the analog signal of channel 2 is output from AOUT2 pin. The 28 bit signal structure is shown in Figure 4. It consists of voice band PCM signals (8 bits each), the generalpurpose latch signal (6 bits total), the power down control signal (1 bit per channel) and empty bits (4 bits). The signal is shifted at a falling edge of the BCLK signal and latched into the internal register when shifted by 28 bits. The start of the PCM data (Channel 1's MSD) is identified at the rising edge of RSYNC. The general purpose latch signal (C3A, C2A, C1A, C3B, C2B, C1B) are output from six latch output pins. When the CPD1 (bit of DIN) = "0", Channel 1 block is in a power down state. When the CPD2 (bit of DIN) = "0", Channel 2 block is in a power down state. DOUT DOUT is a data output pin. The signal consist of a total of 28 bits containing the voice band PCM signals (each channel 8 bits), the echo bit (6 bits for latch signal and 2 bits for power down state indication), and empty bits (4 bits). The output cording format follows ITU-T recommendation on coding law. The output signal is output from Channel 1's MSD bit in a sequential order, synchronizing with the rising edge of the BCLK signal. The first bit of DOUT may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state during power down state. A pull-up resistor must be connected to this pin because it is an open drain output.
Table 1 The Output Cording Format
INPUT/OUTPUT Level + Full scale +0 -0 - Full scale MSD 1 1 0 0 D2 0 1 1 0 D3 0 1 1 0 PCMIN/PCMOUT -law D4 0 1 1 0 D5 0 1 1 0 D6 0 1 1 0 D7 0 1 1 0 D8 0 1 1 0
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C1A, C2A, C3A, C1B, C2B, C3B General-purpose latched output signal. C1A, C2A, C3A, C1B, C2B, C3B bits of DIN are latched using internal timing. These outputs can drive a LSTTL/CMOS device without external resistor. PDN Power down control signal. When PDN is at logic "0" level, both Channel 1 and Channel 2 circuits are in the power down state. Also, all internal latches are in initial state (logic "0" level). TEST1, TEST2, TEST3, TEST4, TEST5, TEST6 These pins are used for device test. These device test pin must be connected to the AG pin.
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Table 2 Condition of DOUT by the Power Control
PDN 0 1 1 1 1 CPD1 0/1 0 1 0 1 CPD2 0/1 0 0 1 1 CH1 PCM Data H 11111111 Operate 11111111 Operate CH2 PCM Data H 11111111 11111111 Operate Operate Latched Data Latched Data CH1 Echo Bit H CH2 Echo Bit H
Table 3 Condition of the Latched Output by the Power Control
PDN 0 1 0/1 CPD1 0/1 0/1 0/1 CPD2 0/1 0/1 0/1 LIN 0 1 C1A, C2A, C3A L Latched Data L C1B, C2B, C3B L Latched Data L
Table 4 Condition of the Analog Output by the Power Control
PDN 0 1 1 1 1 CPD1 0/1 0 1 0 1 CPD2 0/1 0 0 1 1 GSX1 High Impedance High Impedance Operate High Impedance Operate GSX2 High Impedance High Impedance High Impedance Operate Operate AOUT1 High Impedance High Impedance Operate High Impedance Operate AOUT2 High Impedance High Impedance High Impedance Operate Operate SGC *5 Operate Operate Operate Operate
*5 The voltage level of AG with about 50 k
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ML7022 1 k +5 V 2CH Multiplex PCM signal output 2CH Multiplex PCM signal input Master clock & Bit clock input Master clock & Bit clock input Power down control 0: power down/1: operation AIN1 GSX1 AOUT1
1 Semiconductor
APPLICATION CIRCUITS
Channel 1 analog input
Channel 1 analog output AIN2 TEST1 GSX2 TEST2 AOUT2 TEST3 0.1 F TEST4 AG TEST5 DG 1 F + TEST6 VDD 0.1 F SGC
DOUT DIN MCK BCLK XSYNC RSYNC PDN
Channel 2 analog input
Channel 2 analog output
0V
+5 V
C1A C2A C3A C1B C2B C3B
Latch output
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RECOMMENDATIONS FOR ACTUAL DESIGN
* To assure specified electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. * Connect the AG pin and DG pin each other as closely as possible. Connect to the system ground with low impedance. * Unless unavoidable, use short lead type socket. * When mounted on a frame, use electromagnetic shielding, if any electromagnetic emission sources such as power supply transformers surround the device. * Keep the voltage on the VDD pin not lower than -0.3 V even instantaneously to avoid latch-up phenomenon when turning the power on. * Use a low noise power supply (having low level high frequency spike noise or pulse noise) to avoid erroneous operation and the degradation of the characteristics of these device.
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PACKAGE DIMENSIONS
(Unit: mm)
SSOP30-P-56-0.65-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.19 TYP. 5/Dec. 5, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd.
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